This invention relates to a level conversion circuit. More particularly, the present invention relates to an input circuit for converting a signal level of ECL (emitter coupled logic) to a signal level of CMOS (complementary metal oxide semiconductor) and to a low power level conversion input circuit suitable as an input circuit of logic LSI.
Recently, CMOS LSI has come to possess a higher circuit speed than TTL (transistor transistor logic) and it has now become possible for CMOS LSI to be used together with ECL LSI. To use CMOS LSI together with ECL LSI, the input-output signal levels of both LSIs must be matched and in particular, an input circuit for converting a signal of an ECL level (-0.9.about.-1.7 V) to a signal of a CMOS level (0.about.-5 V) is necessary. An example of a CMOS input circuit compatible to ECL is illustrated in FIG. 1. In the drawing, P.sub.1 through P.sub.4 are P-MOS transistors and N.sub.1 through N.sub.9 are N-MOS transistors. A circuit 1 formed by P.sub.1, P.sub.2, N.sub.1, N.sub.2, N.sub.3 is a differential input amplifier, and a circuit 2 formed by N.sub.4, N.sub.5, N.sub.6, N.sub.7 is a level shifter. A circuit 3 formed by P.sub.3, P.sub.4, N.sub.8, N.sub.9 is a buffer. V.sub.DD and V.sub.SS are power source voltages. BIAS.sub.1 determines a constant current value of the differential amplifier 1 while BIAS.sub.2 is applied so as to determine a load resistance. V.sub.bb is a reference voltage applied to determine the logic threshold voltage of the ECL circuit. ECL INPUT and CMOS OUTPUT represent the signal input of the ECL level and the signal output of the CMOS level, respectively. Since the ECL signal has low amplitude, the circuit shown in FIG. 1 uses a differential amplifier for its initial stage to prevent the operation from becoming unstable with respect to the statistical variation of devices and to the fluctuation of temperature and power source voltages. The output of this differential amplifier is further amplified over two stages and is converted to the CMOS level. If the delay time of this circuit is reduced, the current of the differential amplifier must be increased so that the power consumption becomes extremely great. Accordingly, though this circuit can be employed for an RAM (random access memory) or the like having a small number of input signals, it can not be employed for a logic LSI because the number of input signals is great and the power consumption of the input circuit alone becomes as great as several Watts.